1. Field of the Invention
This invention relates in general to a data processing system and more specifically to a system bus having a dynamic timing bridge and a method therefor.
2. Description of the Related Art
In a data processing system having a processor, which may act as a master device, and a memory, which may act as a slave device, timing adjustments may need to be made to the system bus to ensure compliance with timing requirements, such as setup time. By way of example, in certain data processing systems, the master device and the slave device may be connected by a bus. For the slave device to reliably sample data on the bus, the data signal needs to be held steady for a certain minimum time before the data is sampled by the slave device. This time is generally referred to as the setup time.
Conventionally, timing requirements have been addressed at the design stage using static register slices. In particular, a register slice may be used to correct a defective timing path by inserting a cyclic delay and thereby producing an equivalent two-clock-cycle timing path instead of a one-clock-cycle timing path. After the design stage, the designer's choices corresponding to inclusion or exclusion of the register slices are permanent. While these permanent changes work well with the worst-case operating mode, they are less optimal in operating modes that allow more relaxed timing. In particular, because of the permanence of the register slice, each transaction on the bus corresponding to the data processing system would suffer an extra cycle of latency regardless of the need for it.
Thus, there is a need for a system bus having a dynamic timing bridge and a method therefor.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.